@W: BN288 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":178:0:178:5|Register lcd_cs_reg with set has an initial value of 0. Ignoring initial value.  
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT529 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":178:0:178:5|Found inferred clock JLX12832G_lcd|clk_in which controls 185 sequential elements including lcd_dc_reg. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
